GigEx® Ethernet engine
The benefits of offloading Ethernet protocols to hardware
To simplify Gigabit Ethernet implementations, Orange Tree has developed GigEx®, a TCP/IP offload engine (TOE) chip. Read more below about the benefits of this approach, or you can download our white paper with more technical detail on the subject.
Ethernet has become the de facto choice for modern communications networks, and is being increasingly deployed in embedded and industrial networking. There remains a significant design and deployment issue with Ethernet: the high CPU overhead of running a full TCP/IP stack, and high latency when compared to other industrial networking solutions such as CANbus, Profibus and Modbus. As bandwidths increase, the processor spends more of its time handling network frames rather than running user algorithms.
Developers that are looking to introduce or optimize Gigabit Ethernet can defeat the TCP/IP overhead through off-load, and accommodate the many different Ethernet standards (such as Industrial Ethernet and GigE Vision) on a single, low cost universal platform such as the Zest series of boards.
TCP/IP offload engine improves performance
To offload the protocols to hardware, Orange Tree developed GigEx®, a TCP/IP offload engine (TOE) chip that shifts the work away from the user application. It is simple to use, and requires no detailed networking skills, Linux or other software knowledge or complex VHDL/Verilog integration. It achieves high bandwidth, up to full Gigabit Ethernet rates, and requires almost no user FPGA resources. GigEx® supports TCP as well as UDP.
The traditional approach of implementing TCP/IP in software causes bottlenecks and performance degradation, as well as increases in BOM cost and system size. Instead, using a TOE to offload the TCP/IP stack into dedicated hardware, big improvements in transmission bandwidth can be achieved, and latency can be minimised.
Alternative approaches
There are, of course, different ways of handling Gigabit Ethernet, but they all have disadvantages. To briefly review four competing approaches:
| Approach | Ease of integration | Resources required | Performance | Total cost (platform, product, development) |
|---|---|---|---|---|
| Collection of IP cores with libraries running on soft processor in user FPGA | Difficult integration involving both FPGA logic and software | High level of user FPGA resources | Difficult to achieve maximum bandwidth | Very high |
| Third party optimised software stack on embedded CPU | Difficult integration of software | Very high level of CPU processing time | Difficult to achieve maximum bandwidth | High |
| Using an operating system on embedded CPU (for example Linux) | Requires high level of software expertise, and difficult to interface to peripherals | Very high level of CPU processing time | Requires a fast and expensive CPU to achieve maximum bandwidth | Medium |
| UDP core on user FPGA | Difficult integration of FPGA logic | High level of user FPGA resources | Unreliable protocol and unable to use any higher level protocol that requires TCP (e.g. SMB, HTTP) | Low to Medium |
| GigExTM | Simple register and parallel streaming interfaces | Very low level of user FPGA resources | Maximum bandwidth (100MBytes/sec) | Included in cost of each board |
Overall, offloading the Ethernet protocols to the dedicated hardware of GigEx® provides the best solution – with high performance, flexibility, and simplicity of design.
For more technical detail on GigEx® and our approach to Gigabit Ethernet, download our white paper.
