ZestET1 Gigabit Ethernet FPGA Board
The ZestET1 is a low cost, easy to use, very high performance Gigabit Ethernet TCP/IP Offload Engine (TOE) and FPGA Module that provides a universal interface to connect devices quickly to an Ethernet network at Gigabit speed. It sustains a data rate of over 100MBytes/s in each direction, latency is measured at 6µsec and the board can be used for existing and new product designs.
Orange Tree's proprietary GigExpedite chip "GigEx" is a TOE that handles all the Ethernet communications protocols. This leaves the Spartan-3A FPGA completely free for the user's application, and means the user doesn't have to know anything about Ethernet protocols. With the main processing engine implemented in TOE hardware, sustained data rates over 100MBytes/sec are achieved. You can read more about GigEx here.
With its low price point, ease of use and compact form factor (50mm x 75mm), the module is ideally suited to integration in embedded systems and OEM equipment. It features a user programmable Xilinx Spartan-3A FPGA with up to 1.4M system gates that are completely free for user programming.
The FPGA can be programmed from on-board Flash, Ethernet or JTAG, and is capable of running soft-core processors and higher level protocols such as GigE Vision and Industrial Ethernet. It can also be used as a programmable interface to external devices, for processing data on the fly, high speed processing of streaming data and controlling external devices.
- Low cost and easy to use with no detailed Ethernet networking knowledge required
- Offers simple access to very fast data rates over Gigabit Ethernet without having to integrate complex networking hardware and software
- Devices can communicate via Ethernet without using a processor or incurring processor overheads
- Can be quickly and cost-effectively extended to application layer protocols
- More than 100MBytes/s sustained data rate in each direction over Gigabit Ethernet
- High reliability and high stability hardware Gigabit Ethernet TOE for UDP and TCP/IP offload
- User programmable companion Spartan-3A FPGA supports low cost, soft core processor implementation and application layer protocols
- Windows and Linux software support for configuring and communicating with the user FPGA
- Logic cores for all FPGA interfaces
- Reference designs (including C, VHDL and Verilog source)
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Discounts are available for volume orders, students, and non-commercial university projects